Manuj Verma
7Patents
5h-index
11Co-inventors
56Inventor score
Filing activity: Oct 11, 2005 → May 13, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10031986B1 | System and method for creating a spice deck for path-based analysis of an electronic circuit design using a stage-based technique | Physics | 14 | Active |
| US9589096B1 | Method and apparatus for integrating spice-based timing using sign-off path-based analysis | Physics | 10 | Active |
| US9881123B1 | Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact | Physics | 8 | Active |
| US7464349B1 | Method and system or generating a current source model of a gate | Physics | 7 | Active |
| US10289774B1 | Systems and methods for reuse of delay calculation in static timing analysis | Physics | 5 | Active |
| US9529962B1 | System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design | Physics | 4 | Active |
| US11023636B1 | Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.