Hybrid copper structure for advance interconnect usage
US10290580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.