Gate input protection for devices and systems comprising high power E-mode GaN transistors
US10290623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2016 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
Abstract
An integrated gate protection device P for a GaN power transistor D1 provides negative ESD spike protection. Protection device P comprises a smaller gate width wg enhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D1, and the source of Pm is connected to the intrinsic source of D1. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors P1 to Pn, connected in series, it turns on when the gate input voltage applied to the drain of P1 goes negative by more than the sum of the threshold voltages of P1 to Pn. The combined gate width of P1 to Pn is selected to limit the gate voltage excursion of D1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.