High voltage electrostatic discharge (ESD) bipolar integrated in a vertical field-effect transistor (VFET) technology and method for producing the same
US10290626B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of integrating a HV ESD PNP bipolar transistor in a VFET process and the resulting devices are provided. Embodiments include forming a DNW region in a portion of a p-sub; forming a HVPDDD region in a portion of the DNW region; forming a first and a second NW in a portion of the DNW region, the second NW between the first NW and the HVPDDD region and laterally separated from the HVPDDD region; forming a PW in a portion of the HVPDDD region; forming an N+ implant in a portion of the first NW and a P+ implant in a portion of the PW; forming a first, a second and a third fin structures over the first and the second NW and the PW, respectively; and forming a N+ S/D, a P+ S/D and a P+ S/D over the first, the second and the third fin structures, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.