High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same
US10290679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2018 |
| Grant date | May 14, 2019 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalable method of forming an integrated high-density STT-MRAM with a 3D array of multi-level MTJs and the resulting devices are provided. Embodiments include providing a Si substrate of an X-density STT-MRAM having an array of interconnect stacks; forming a level of a MTJ structure on each of a first interconnect stack and a second interconnect stack, wherein (X−1) defines a number of interconnect stacks between the first and the second interconnect stacks; forming a via on each interconnect stack without a MTJ structure; forming a metal layer on each MTJ structure and via on the level; repeating the forming of the MTJ structure, the via, and the metal layer one interconnect stack laterally shifted until the level of the MTJ structure equals X, only forming the MTJ structure at that level; forming a bit line over the substrate; and connecting the bit line to each MTJ structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.