Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof
US10297319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2017 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.