Process for the manufacture of a semiconductor element comprising a layer for trapping charges
US10297464B2 · kind B2 · utility
1Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2016 |
| Grant date | May 21, 2019 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76254
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.