Preemptive cache management policies for processing units
US10303602B2 · kind B2 · utility
2Cited by
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19Claims
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Key dates
| Filing date | Mar 31, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes at least one central processing unit (CPU) core, at least one graphics processing unit (GPU) core, a main memory, and a coherence directory for maintaining cache coherence. The at least one CPU core receives a CPU cache flush command to flush cache lines stored in cache memory of the at least one CPU core prior to launching a GPU kernel. The coherence directory transfers data associated with a memory access request by the at least one GPU core from the main memory without issuing coherence probes to caches of the at least one CPU core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.