Increasing invalid to modified protocol occurrences in a computing system
US10303605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.