Parallelizing timing-based operations for circuit designs
US10303833B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.