Method for low power operation and test using DRAM device
US10304522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2017 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jan 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Big data analysis using low power circuit design including storing a plurality of data bits in a plurality of cells on a bitline of a dynamic random access memory (DRAM), wherein each data bit corresponds to a test result, and wherein each of the plurality of cells on the bitline is associated with a different wordline; precharging the bitline to a midpoint voltage between a low voltage corresponding to a low data bit and a high voltage corresponding to a high data bit; activating, at the same time, each wordline associated with each of the plurality of cells on the bitline, wherein activating each wordline causes a voltage to be applied to the bitline from each of the plurality of cells; and measuring a resulting voltage on the bitline to obtain a value corresponding to a percentage of the test results that indicate a passing test result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.