David P. Paulsen
106Patents
9h-index
35Co-inventors
76Inventor score
Filing activity: Oct 10, 2007 → May 10, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8525245B2 | eDRAM having dynamic retention and performance tradeoff | Electricity | 20 | Active |
| US8549363B2 | Reliability and performance of a system-on-a-chip by predictive wear-out based activation of functional components | Physics | 15 | Active |
| US8816470B2 | Independently voltage controlled volume of silicon on a silicon on insulator chip | Electricity | 15 | Active |
| US8492220B2 | Vertically stacked FETs with series bipolar junction transistor | Electricity | 12 | Active |
| US10043568B1 | Optimizing data approximation analysis using low power circuitry | Physics | 10 | Active |
| US9024387B2 | FinFET with body contact | Electricity | 10 | Active |
| US8754417B2 | Vertical stacking of field effect transistor structures for logic gates | Electricity | 10 | Active |
| US10037792B1 | Optimizing data approximation analysis using low power circuitry | Physics | 10 | Active |
| US9916890B1 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Physics | 10 | Active |
| US8435851B2 | Implementing semiconductor SoC with metal via gate node high performance stacked transistors | Electricity | 7 | Active |
| US8492903B2 | Through silicon via direct FET signal gating | Electricity | 7 | Active |
| US7514276B1 | Aligning stacked chips using resistance assistance | Electricity | 6 | Active |
| US10418094B2 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Physics | 6 | Active |
| US10304522B2 | Method for low power operation and test using DRAM device | Physics | 6 | Active |
| US8574982B2 | Implementing eDRAM stacked FET structure | Electricity | 6 | Active |
| US9245884B1 | Structure for metal oxide semiconductor capacitor | Electricity | 5 | Active |
| US9018713B2 | Plural differential pair employing FinFET structure | Electricity | 5 | Active |
| US8809156B1 | Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications | Electricity | 5 | Active |
| US9343464B2 | Implementing eDRAM stacked FET structure | Electricity | 5 | Active |
| US7868391B2 | 3-D single gate inverter | Electricity | 4 | Active |
| US7541829B1 | Method for correcting for asymmetry of threshold voltage shifts | Physics | 4 | Active |
| US8921199B1 | Precision IC resistor fabrication | Electricity | 4 | Active |
| US8890083B2 | Soft error detection | Physics | 4 | Active |
| US8138054B2 | Enhanced field effect transistor | Electricity | 3 | Active |
| US10236050B2 | Optimizing data approximation analysis using low power circuitry | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.