Erase speed based word line control
US10304551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, methods, and computer program products are disclosed for erase depth control. One apparatus includes a block of non-volatile storage cells. A controller is configured to perform a first erase operation on a block of non-volatile storage cells. A controller for a block is configured to determine a first set of storage cells of the block having a faster erase speed than a second set of storage cells of the block based on a verify voltage threshold. A controller for a block is configured to perform a second erase operation on the block using different voltages for a first set of storage cells and a second set of storage cells of the block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.