Nanoscale interconnect array for stacked dies
US10304803B2 · kind B2 · utility
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3References
12Claims
0Family size
Assignee
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Key dates
| Filing date | May 5, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | May 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.