Forcing core low power states in a processor
US10310588B2 · kind B2 · utility
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27References
17Claims
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Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.