Pre-silicon design rule evaluation
US10311200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.