Secure system memory training
US10311236B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Apr 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for performing secure system memory training are disclosed. In one embodiment, a system includes a boot media, a security processor with a first memory, a system memory, and one or more main processors coupled to the system memory. The security processor is configured to retrieve first data from the boot media and store and authenticate the first data in the first memory. The first data includes a first set of instructions which are executable to retrieve, from the boot media, a configuration block with system memory training parameters. The security processor also executes a second set of instructions to initialize and train the system memory using the training parameters. After training the system memory, the security processor retrieves, authenticates, and stores boot code in the system memory and releases the one or more main processors from reset to execute the boot code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.