Oswin E. Housty
14Patents
5h-index
14Co-inventors
59Inventor score
Filing activity: Jan 21, 2004 → Nov 15, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7924637B2 | Method for training dynamic random access memory (DRAM) controller timing delays | Physics | 22 | Active |
| US7251744B1 | Memory check architecture and method for a multiprocessor computer system | Physics | 15 | Expired |
| US8850155B2 | DDR 2D Vref training | Physics | 14 | Active |
| US8307198B2 | Distributed multi-core memory initialization | Physics | 13 | Active |
| US9214199B2 | DDR 2D Vref training | Physics | 8 | Active |
| US9183125B2 | DDR receiver enable cycle training | Physics | 5 | Active |
| US8566570B2 | Distributed multi-core memory initialization | Physics | 4 | Active |
| US8392640B2 | Pre-memory resource contention resolution | Physics | 3 | Active |
| US10311236B2 | Secure system memory training | Physics | 2 | Active |
| US8055939B2 | Memory control device and methods thereof | Physics | 1 | Active |
| US11176986B2 | Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training | Emerging Cross-Sectional Technologies | 1 | Active |
| US7971098B2 | Bootstrap device and methods thereof | Physics | 1 | Active |
| US11682445B2 | Memory context restore, reduction of boot time of a system on a chip by reducing double data rate memory training | Emerging Cross-Sectional Technologies | 0 | Active |
| US8176303B2 | Multiprocessor communication device and methods thereof | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.