Self-aligned double patterning method
US10312088B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 20, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Feb 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned double patterning method includes the steps of forming line structures spaced apart from each other in a first direction on a mask layer, forming dielectric layer on the line structures, performing an etch back process so that the top surfaces of the line structures and the dielectric layer are flush, forming layer structure with same material as the line structures on the line structures and the dielectric layer, forming spacers spaced apart from each other in a second direction on the layer structure, and performing an etch process with the spacers as an etch mask to pattern the line structures and the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.