Field effect transistor with stacked nanowire-like channels and methods of manufacturing the same
US10312152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2017 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Nov 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions and a dielectric separation region extending completely between first and second nanowire-like channel regions of the stack. The nFET and the pFET each also include a source electrode and a drain electrode on opposite sides of the fin, and a gate stack extending along a pair of sidewalls of the stack of nanowire-like channel regions. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions. The channel heights of the nanowire-like channel regions of the partial GAA nFET and the partial GAA pFET are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.