Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication

US10312247B1 · kind B1 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Serguei Jourba · Aix-en-Provence, FR
• Catherine Decobert · Saint-Maximin-la-Sainte-Baume, FR
• Feng Zhou · Ann Arbor, US
• Jinho Kim · Seoul, KR
• Xian Liu · Sunnyvale, US
• Nhan Do · Saratoga, US

Key dates

• Filing date: Mar 22, 2018
• Grant date: Jun 4, 2019
• Expiry date: Mar 22, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.