Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same
US10312256B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) stacked semiconductor structure is provided. A substrate having an array area and a peripheral area is provided, and several patterned multi-layered stacks above the substrate are formed in the array area. The patterned multi-layered stacks are spaced apart from each other, and channel holes are formed between the patterned multi-layered stacks disposed adjacently. A charge trapping layer is formed on the patterned multi-layered stacks and deposited in the channel holes as liners. A polysilicon channel layer is deposited along the charge trapping layer, and conductive pads are formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks. The polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), wherein the second thickness (t2) is larger than the first thickness (t1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.