Network flow based framework for clock tree optimization
US10318684B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2015 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Mar 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.