Patent · US Active

Graphics with early stencil test

US10319138B2 · kind B2 · utility

0Cited by

1References

16Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Vasanth Ranganathan · Cameron Park, US
Saikat Mandal · Sacramento, US
Prasoonkumar Surti · Folsom, US
Abhishek R. Appu · Cameron Park, US
Andrew S. Downsworth · Folsom, US
Vamsee Vardhan Chivukula · Folsom, US
Akshay R. Chada · Folsom, US
Karol A. Szerszen · Hillsboro, US
Joydeep Ray · Folsom, US
Bryon T. Rogers · Folsom, US

Key dates

Filing date	Apr 1, 2017
Grant date	Jun 11, 2019
Priority date	—
Expiry date	Apr 1, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06T1/20
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An embodiment of graphics apparatus may include a coarse depth tester to perform a coarse depth test on a block of pixels, and a stencil tester to perform a stencil test on the block of pixels. The stencil tester may be further configured to perform the stencil test in parallel with the coarse depth test. Other embodiments are disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.