Package including multiple semiconductor devices
US10319670B2 · kind B2 · utility
1Cited by
13References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Oct 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.