High voltage transistor using buried insulating layer as gate dielectric

US10319827B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Elliot John Smith · Dresden, DE
• Nigel Chan · Sunnyvale, US

Key dates

• Filing date: Jul 12, 2017
• Grant date: Jun 11, 2019
• Expiry date: Feb 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.