Scoped persistence barriers for non-volatile memories
US10324650B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.