Method of wafer thinning and realizing backside metal structures

US10325804B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Oliver Hellmund · Straubing, DE
• Johannes Baumgartl · Arnoldstein, AT
• Iris Moder · Villach, AT
• Ingo Muri · Villach, AT
• Thomas Neidhart · Klagenfurt, AT
• Hans-Joachim Schulze · Taufkirchen, DE

Key dates

• Filing date: Dec 29, 2017
• Grant date: Jun 18, 2019
• Expiry date: Dec 29, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/30608
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming openings partially filled with a sacrificial material, where the openings extend into a semiconductor substrate from a first side. A void region is formed in a central region of the openings. An epitaxial layer is formed over the first side of the semiconductor substrate and the openings, where the epitaxial layer covers the void region. From a second side of the semiconductor substrate opposite to the first side, the semiconductor substrate is thinned to expose the sacrificial material. The sacrificial material in the openings is removed and the epitaxial layer is exposed. A conductive material is deposited on the exposed surface of the epitaxial layer.