Patent · US Active

Semiconductor packages and methods of fabrication thereof

US10325834B2 · kind B2 · utility

0Cited by
3References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 9, 2017
Grant dateJun 18, 2019
Priority date
Expiry dateSep 2, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/206
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.