Advanced transistors with punch through suppression

US10325986B2 · kind B2 · utility

Assignee

• Mie Fujitsu Semiconductor Limited · JP

Inventors

• Lucian Shifren · San Jose, US
• Pushkar Ranade · Los Gatos, US
• Paul E. Gregory · Palo Alto, US
• Sachin R. Sonkusale · Los Gatos, US
• Weimin Zhang · San Jose, US
• Scott E. Thompson · Gainesville, US

Key dates

• Filing date: Oct 20, 2016
• Grant date: Jun 18, 2019
• Expiry date: Oct 20, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.