Gate all around device and fabrication thereof
US10325993B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Sep 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/122
Abstract
A device includes a nanowire, a gate dielectric layer and a gate electrode. The nanowire has a sidewall. The gate dielectric layer surrounds the nanowire. The gate electrode surrounds the gate dielectric layer and separated from the nanowire. The gate electrode comprises a sloped sidewall inclined with respect to the sidewall of the nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.