Stacked memory device and a memory chip including the same
US10331354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Jun 8, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.