Tracking stores and loads by bypassing load store units
US10331357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2016 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.