Kai Troester
14Patents
2h-index
29Co-inventors
50Inventor score
Filing activity: Oct 22, 2010 → Nov 5, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8392757B2 | Method and apparatus for processing load instructions in a microprocessor having an enhanced instruction decoder and an enhanced load store unit | Physics | 2 | Active |
| US11048506B2 | Tracking stores and loads by bypassing load store units | Physics | 2 | Active |
| US11144324B2 | Retire queue compression | Physics | 1 | Active |
| US10331357B2 | Tracking stores and loads by bypassing load store units | Physics | 1 | Active |
| US11169812B2 | Throttling while managing upstream resources | Physics | 1 | Active |
| US11023241B2 | Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines | Physics | 0 | Active |
| US9367310B2 | Stack access tracking using dedicated table | Physics | 0 | Active |
| US11467838B2 | Fastpath microcode sequencer | Physics | 0 | Active |
| US11294724B2 | Shared resource allocation in a multi-threaded microprocessor | Physics | 0 | Active |
| US9292292B2 | Stack access tracking | Physics | 0 | Active |
| US11144353B2 | Soft watermarking in thread shared resources implemented through thread mediation | Physics | 0 | Active |
| US12204911B2 | Retire queue compression | Physics | 0 | Active |
| US11847463B2 | Masked multi-lane instruction memory fault handling using fast and slow execution paths | Physics | 0 | Active |
| US12032965B2 | Throttling while managing upstream resources | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.