Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time

US10331582B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ishwar Bhati · Bengaluru, IN
• Huichu Liu · Santa Clara, US
• Jayesh Gaur · Bengaluru, IN
• Kunal Kishore Korgaonkar · Bengaluru, IN
• Sasikanth Manipatruni · Ithaca, US
• Sreenivas Subramoney · Bengaluru, IN
• Tanay Karnik · Portland, US
• Hong Wang · Santa Clara, US
• Ian A. Young · Portland, US

Key dates

• Filing date: Feb 13, 2017
• Grant date: Jun 25, 2019
• Expiry date: Jul 1, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/222
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.