Patent · US Active

False path timing exception handler circuit

US10331826B2 · kind B2 · utility

2Cited by

4References

18Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Wilson Pradeep · Savanuru, IN
Prakash Narayanan · Bengaluru, IN
Saket Jalan · Bengaluru, IN

Key dates

Filing date	Jun 22, 2017
Grant date	Jun 25, 2019
Priority date	—
Expiry date	Jun 24, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/17
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.