Semiconductor memory device
US10332581B2 · kind B2 · utility
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1References
13Claims
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Assignee
Inventors
Key dates
| Filing date | Mar 9, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Mar 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.