Memory block usage based on block location relative to array edge
US10332608B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 30, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.