Method for fabricating semiconductor device with strained silicon structure
US10332750B2 · kind B2 · utility
0Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Nov 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.