Self-organizing barrier layer disposed between a metallization layer and a semiconductor region

US10332793B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Werner Robl · Regensburg, DE
• Michael Fugger · Wien, AT
• Carsten Schaeffer · Annenheim, AT
• Michael Nelhiebel · Villach, AT
• Klemens Pruegl · Regensburg, DE

Key dates

• Filing date: Nov 30, 2015
• Grant date: Jun 25, 2019
• Expiry date: Nov 30, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/53266
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.