Werner Robl
25Patents
5h-index
67Co-inventors
68Inventor score
Filing activity: Sep 28, 2001 → Jul 10, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6720212B2 | Method of eliminating back-end rerouting in ball grid array packaging | Electricity | 69 | Expired |
| US6734097B2 | Liner with poor step coverage to improve contact resistance in W contacts | Electricity | 18 | Expired |
| US8148257B1 | Semiconductor structure and method for making same | Electricity | 11 | Active |
| US6866943B2 | Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level | Emerging Cross-Sectional Technologies | 6 | Expired |
| US8338317B2 | Method for processing a semiconductor wafer or die, and particle deposition device | Electricity | 5 | Active |
| US8334202B2 | Device fabricated using an electroplating process | Electricity | 2 | Active |
| US8330274B2 | Semiconductor structure and method for making same | Electricity | 2 | Active |
| US8665054B2 | Semiconductor component with coreless transformer | Electricity | 1 | Active |
| US10741402B2 | Electronic device, electronic module and methods for fabricating the same | Electricity | 1 | Active |
| US6794282B2 | Three layer aluminum deposition process for high aspect ratio CL contacts | Electricity | 1 | Expired |
| US11615963B2 | Electronic device, electronic module and methods for fabricating the same | Electricity | 0 | Active |
| US11276624B2 | Semiconductor device power metallization layer with stress-relieving heat sink structure | Electricity | 0 | Active |
| US8786085B2 | Semiconductor structure and method for making same | Electricity | 0 | Active |
| US9418937B2 | Integrated circuit and method of forming an integrated circuit | Electricity | 0 | Active |
| US9425146B2 | Semiconductor structure and method for making same | Electricity | 0 | Active |
| US11171049B2 | Semiconductor device and a method of forming the semiconductor device | Electricity | 0 | Active |
| US6960306B2 | Low Cu percentages for reducing shorts in AlCu lines | Electricity | 0 | Expired |
| US10332793B2 | Self-organizing barrier layer disposed between a metallization layer and a semiconductor region | Electricity | 0 | Active |
| US10648096B2 | Electrolyte, method of forming a copper layer and method of forming a chip | Electricity | 0 | Active |
| US8072071B2 | Semiconductor device including conductive element | Electricity | 0 | Active |
| US7909978B2 | Method of making an integrated circuit including electrodeposition of metallic chromium | Chemistry; Metallurgy | 0 | Active |
| US7974120B2 | Spin device | Electricity | 0 | Active |
| US6943114B2 | Integration scheme for metal gap fill, with fixed abrasive CMP | Emerging Cross-Sectional Technologies | 0 | Expired |
| US8759207B2 | Semiconductor structure and method for making same | Electricity | 0 | Active |
| US10446469B2 | Semiconductor device having a copper element and method of forming a semiconductor device having a copper element | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.