Semiconductor package structure and method for manufacturing the same
US10332862B2 · kind B2 · utility
5Cited by
2References
30Claims
0Family size
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Key dates
| Filing date | Sep 7, 2017 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Sep 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.