Vertical field-effect transistors including uniform gate lengths

US10332983B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Choonghyun Lee · Rensselaer, US
• Juntao Li · Cohoes, US
• Heng Wu · Guilderland, US
• Peng Xu · Guilderland, US

Key dates

• Filing date: Mar 26, 2018
• Grant date: Jun 25, 2019
• Expiry date: Mar 26, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/518
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Vertical field-effect transistors are fabricated while controlling gate length by causing enhanced oxidation of silicon germanium regions on parallel semiconductor fin channel regions. Oxidation of the silicon germanium region is accompanied by volume expansion and condensation. Shared or non-shared gate structures are formed on the sidewalls of the semiconductor fin channel regions. A dielectric liner may be incorporated with self-aligned oxide regions to form a composite spacer for providing electrical isolation of the top source/drain regions.