Method and structure of forming fin field-effect transistor without strain relaxation

US10332999B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kangguo Cheng · Schenectady, US
• Juntao Li · Cohoes, US
• Choonghyun Lee · Rensselaer, US
• Peng Xu · Guilderland, US
• Heng Wu · Guilderland, US

Key dates

• Filing date: Mar 9, 2018
• Grant date: Jun 25, 2019
• Expiry date: Mar 9, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a semiconductor device includes patterning a strained semiconductor layer on a substrate into at least one strained fin, forming a plurality of dummy gates spaced apart from each other on the at least one strained fin, forming a spacer layer on the plurality of dummy gates, and on part of the at least one strained fin between the plurality of dummy gates, growing a plurality of source/drain regions on exposed portions of the at least one strained fin, removing the spacer layer from the part of the at least one strained fin between the plurality of dummy gates, and converting the part of the at least one strained fin between the plurality of dummy gates into at least one oxide.