Self-gating pulsed flip-flop
US10333500B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2018 |
| Grant date | Jun 25, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17744
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a latch configured to update a stored state of the latch in response to an input data signal and a pulsed clock signal. The circuit includes a pulse generator configured to generate the pulsed clock signal based on an input clock signal, the input data signal, and a feedback signal indicative of a stored state of the latch. The pulse generator may be configured to generate a pulse enable signal based on the input data signal, the input clock signal, and the feedback signal. The pulsed clock signal may be based on the pulse enable signal and the input clock signal. The pulse generator may generate the pulsed clock signal to have a pulse of a first signal level in response to an indication that the stored state of the latch needs to change and generates the pulsed clock signal to have a second signal level, otherwise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.