Patrick J. Shyvers
13Patents
2h-index
16Co-inventors
43Inventor score
Filing activity: Jan 26, 2017 → Dec 20, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10431517B2 | Arrangement and thermal management of 3D stacked dies | Electricity | 4 | Active |
| US10509752B2 | Configuration of multi-die modules with through-silicon vias | Emerging Cross-Sectional Technologies | 3 | Active |
| US12306754B2 | Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches | Physics | 1 | Active |
| US12393518B2 | Deterministic mixed latency cache | Physics | 0 | Active |
| US10333500B1 | Self-gating pulsed flip-flop | Electricity | 0 | Active |
| US11189540B2 | Arrangement and thermal management of 3D stacked dies | Electricity | 0 | Active |
| US11776599B2 | Encoded enable clock gaters | Physics | 0 | Active |
| US11164807B2 | Arrangement and thermal management of 3D stacked dies | Electricity | 0 | Active |
| US12266585B2 | Arrangement and thermal management of 3D stacked dies | Electricity | 0 | Active |
| US10311191B2 | Memory including side-car arrays with irregular sized entries | Physics | 0 | Active |
| US12009047B2 | Systems and methods for continuous wordline monitoring | Physics | 0 | Active |
| US11782897B2 | System and method for multiplexer tree indexing | Physics | 0 | Active |
| US11308057B2 | System and method for multiplexer tree indexing | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.