Highly accurate defect identification and prioritization of fault locations

US10338137B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Sameer Chakravarthy Chillarige · Bengaluru, IN
• Anil Malik · New Delhi, IN
• Sharjinder Singh · Delhi, IN
• Joseph Michael Swenton · Owego, US

Key dates

• Filing date: Jul 20, 2016
• Grant date: Jul 2, 2019
• Expiry date: Sep 2, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3193
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for defect identification for an integrated circuit includes determining a defect ranking technique, applying at least two defect identification techniques and generating a defect report corresponding to each technique, comparing the defect reports and generating probable defect locations, prioritizing the probable defect locations according to the defect ranking technique; and generating a report of the prioritized probable defect locations.