Mechanism for reducing page migration overhead in memory systems
US10339067B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.