Integrated circuit substrate having configurable circuit elements
US10340197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2017 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Jun 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A die includes a plurality of dielectric landings and a conductive material distributed across one or more of the plurality of dielectric landings. Each one of the plurality of dielectric landings electrically separates two conductive landings associated with the one of the plurality of dielectric landings. The conductive material establishes an electrical connection between the two conductive landings associated with the one or more of the plurality of dielectric landings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.