Semiconductor memory device and fabrication method thereof
US10340282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2018 |
| Grant date | Jul 2, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.